1. Field of the Invention
The present invention relates to the field of fabricating semiconductor devices, and, more particularly, to etch processes for forming trenches and vias in a dielectric material for the formation of metallization layers.
2. Description of the Related Art
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Typically, such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, filled with an appropriate metal. The vias provide electrical connection between two neighboring stacked metallization layers, wherein the metal-containing lines and vias may also be commonly referred to as interconnects.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase and the dimensions of the individual lines and vias may be reduced as the number of circuit elements per chip area becomes larger. The fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of a plurality of stacked metallization layers. As the complexity of integrated circuits advances and brings about the necessity for conductive lines that can withstand moderately high current densities, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum with a metal that allows higher current densities and hence allows a reduction in the dimensions of the interconnections and thus the number of stacked metallization layers. For example, copper and alloys thereof are materials that are used to increasingly replace aluminum, due to their superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum. Despite these advantages, copper and copper alloys also exhibit a number of specifics regarding the processing and handling in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures. Consequently, in manufacturing metallization layers including copper, the so-called inlaid or damascene technique (single and dual) is preferably used, wherein a dielectric layer is first applied and then patterned to receive trenches and/or vias which are subsequently filled with copper or copper alloys.
It turns out that the process of patterning vias and trenches in the dielectric layer, which is frequently provided in the form of a low-k dielectric material, may significantly affect the overall damascene process flow and may also have an impact on the finally obtained copper-based connection, since, for instance, a variation of the trench width and depth may result in a different conductivity and thus a different electric performance of the device in terms of operating speed and reliability. Therefore, the various manufacturing steps, including advanced lithography and etch techniques, have to be thoroughly monitored. Ideally, the effect of each individual process step on each substrate would be detected by measurement and the substrate under consideration would be released for further processing only if the required specifications were met. However, such a process control strategy is not practical since measuring the effects of certain processes may require relatively long measurement times, frequently ex situ, or may even necessitate the destruction of the sample. Moreover, immense effort, in terms of time and equipment, would have to be made on the metrology side to provide the required measurement results. Additionally, utilization of the process tool would be minimized since the tool would be released only after the provision of the measurement result and its assessment.
Thus, the lithography process providing the required etch mask for patterning the dielectric material may frequently be controlled on the basis of an appropriate advanced process control (APC) strategy. Highly scaled semiconductor devices having critical dimensions of 100 nm and significantly less in the device level may also require highly scaled metal lines and vias in the wiring level of the device. Consequently, the formation of metal lines and vias may require sophisticated lithography processes. However, post-lithography processes and particularly the etch process for actually forming the vias and trenches on the basis of the resist mask or hard mask obtained by lithography may also affect the process output. For example, an etch process that is typically performed after a critical lithography process, such as the patterning of the low-k dielectric material in the metallization layers typically used in advanced semiconductor devices, may have a significant influence on the finally obtained dimension of the metal line or via under consideration. In modern semiconductor plants, a plurality of etch tools or at least a plurality of different process chambers are usually used for performing the same process recipe according to availability and process flow management in the plant. Although each of these different tools or process chambers may be operated on the basis of the same parameter settings with respect to, for example, plasma power, pressure, gas flow rates and the like, a variation of the critical dimension may be observed, although advanced control schemes in the preceding lithography process may be used.
In view of the situation described above, there exists a need for a technique that enables an enhanced control strategy for etch processes, wherein one or more of the problems identified above may be avoided or the effects thereof at least be significantly reduced.